1. Field of the Invention:
The present invention is in the field of power semiconductor devices generally and is directed to overvoltage protection of thyristors specifically.
2. Description of the Prior Art:
Typically overvoltage protection of a thyristor employs an avalanche current in the gate region to trigger the thyristor. The avalanching is achieved by etching a deep well, approximately 10 mils, in the gate region, during processing of a silicon wafer, the etching usually occurring after an aluminum diffusion and before a gallium diffusion is carried out. The avalanche voltage is determined by the depth and profile of the etched well.
The use of avalanching for self-protection will succeed or fail depending upon whether the avalanche voltage is less than or more than the edge breakdown voltage of the device.
The use of avalanching necessarily involves some derating of the electrical parameters of the device. Particularly, there is a derating of the forward blocking voltage, V.sub.DRM, along with an attendant increase in forward drop, V.sub.F, for the same V.sub.DRM.
A major shortcoming of the prior art etched well protection system is the requirement that the well be formed relatively early in the wafer fabrication processing, before the blocking capability of the thyristor can be measured.
Another shortcoming of this prior art is the difficulty of controlling the subsequent gallium diffusion, after the etching of the well, to obtain the necessary curvature of the forward blocking junction.
The deep well prior art is discussed in "Thyristors With Overvoltage Self-Protection", J. X. Przybysz and E. S. Schlegel, 1981 IEDM, pgs. 410-413.
Two other prior art methods of overvoltage protection are (1) a thinned anode base for controlling V.sub.BO location and voltage level, and (2) using a curved forward blocking junction.
Both of these methods require building in the protection before the thyristor is completed and its parameters measured.
A deep well that results in avalanching at 2800 volts provides no protection to a thyristor which experiences edge breakdown at 2700 volts. On the other hand, a 2800 volt avalanche is too much derating for a thyristor which could block 3200 volts.
The deep well avalanche method leaves the process engineer the choice between high yield with greatly derated thyristors or a low yield with only slightly derated devices.
The curved junction technique frequently results in low yields due to the diffuculty in masking p-type diffusions.
The thin anode base and curved junction technique for achieving overvoltage protection are discussed in "Controlled Thyristor Turn-On For High DI/DT Capability", V. A. K. Temple, 1981 IEDM, pgs. 406-409.
The use of auxiliary thyristors and inhomogeneous or heterogeneous doping of the n-type base region is discussed in "A Thyristor Protected Against di/dt Failure At Breakdown Turn-On", P. Voss, Solid State Electronics, 1974, Vol. 17, pgs. 655-661.
U.S. Pat. No. 4,003,072 teaches curved junctions as a means of overvoltage protection.
"A New Bipolar Transistor-GAT", Hisao Kondo and Yoshinori Yukimoto, IEEE Transactions On Electronic Devices, Vol. Ed. 27 No. 2, Feb. 1980, pgs. 373-379 is a typical example of prior art teachings of a transistor in which the base region has portions extending deeper into the collector region than the remainder of the base region to contact the depletion region.
Application Ser. No. 190,699 filed Sept. 25, 1980, now abandoned, is an example of several applications filed in which the p-type base region of a thyristor has spacedapart portions extending into the n-type base region to contact the depletion region.
Application Ser. No. 357,106, filed Mar. 3, 1982, now abandoned, teaches providing overvoltage protection in a thyristor by pulsing the center of a gating region of a thyristor with a laser thereby deforming the blocking junction and resulting in a portion of the p-type base extending into the n-type base region.